1. Field of the Invention
The present invention relates to a voltage control circuit and a semiconductor device. More particularly, the present invention relates to a voltage control circuit capable of precisely controlling a target to a constant voltage and a semiconductor device including the same.
2. Description of the Related Art
A non-volatile semiconductor memory device operates so that data is written by a programming operation in which a charge is injected into a gate of a memory cell transistor, and is erased by an erase operation in which the charge is removed from the gate. In programming and erasing, the gate, drain and source of the memory cell transistor are supplied with voltages based on operations.
Generally, the injecting of the charge into the gate and the removing thereof need a voltage that is higher than an external power supply voltage supplied from the outside of the non-volatile semiconductor memory device. The high voltage is generated by a booster circuit that boosts the external power supply voltage. The boosted voltage generated by the booster circuit may be dropped due to a current consumption caused in erasing or programming of a memory cell array circuit. It is thus required to monitor the boosted voltage and check whether the given voltage is maintained as needed. A voltage control circuit is used to meet the requirement. This kind of voltage control circuit is proposed in Japanese Patent Application Publication No. 60259979 and U.S. Pat. No. 5,291,446.
There is another voltage control circuit with a capacitance dividing circuit for high-voltage control. FIG. 1 shows a conventional voltage control circuit including a capacitance dividing circuit. As shown in FIG. 1, a conventional voltage control circuit 1 includes a PMOS transistor 2, NMOS transistors 3 through 5, a comparator circuit 6, select transistors 7 through 12, capacitors CA and CB, and capacitors CC through CC32. The capacitor CC has a capacitance denoted as CC, and the capacitor CCk (for example, CC16) has a capacitance equal to k*CC (for example, 16CC). A reference number 13 indicates an internal booster circuit. The select transistors 7 through 12 are respectively NMOS transistors. Symbols Cpara denote source/drain junction parasitic capacitances of the select transistors 7 through 12 (hereinafter, simply referred to as junction parasitic capacitance).
The capacitors CC through CC32 are respectively connected to a node N1 via the select transistors 7 through 12. A divided voltage VPPDIV is produced by capacitance-dividing a boosted voltage VPP. The comparator circuit 6 compares a reference voltage VREF and the divided voltage VPPDIV, and outputs a resultant signal Vout. When the divided voltage VPPDIV is higher than the reference voltage VREF, the signal Vout is, for example, high. This means that the boosted voltage is too high and is thus subjected to a discharge operation that decreases the boosted voltage.
The step programming method binary-counts signals SEL1 through SEL6 that respectively control the gates of the select transistors 7 through 12, so that the boosted voltage VPP can be raised in an equal stepwise fashion. The target voltage of the boosted voltage VPP is calculated in an ideal circuit as follows:VPP=VREF(1+(CB+(CC+2CC+ . . . ))/CA)   (1)
However, since the select transistors 7 through 12 have the junction parasitic capacitances Cpara, the boosted voltage VPP that can be actually produced is written as follows:VPP=VREF(1+(CB+(CC+2CC+ . . . )+Cpara)/CA)   (2)
The junction parasitic capacitances Cpara of the select transistors 7 through 12 result from the layout. Therefore, it is very difficult to make the boosted voltage VPP equal to the target voltage. As described before, the junction parasitic capacitances of the select transistors increase as an increased number of select transistors is used. For instance, in a case where a capacitance of 3CC is added to the node N1, the signals SEL1 and SEL2 are both high (transistors 7 and 8 are turned ON), and the other transistors are OFF. This causes all the junction capacitances of the four OFF-state transistors corresponding to the unused capacitors CC4 through CC32 to be added to the node N1. This makes it difficult for the conventional voltage control circuit to control and maintain the constant voltage with a precision equal to mV. Thus, the boosted voltage VPP cannot be controlled precisely.
Further, a large total capacitance in the voltage control circuit 1 needs a large size of the reset transistor 3, which may have a leakage current in the OFF state. This makes it difficult to constantly maintain the divided voltage for a long time.